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xicor, inc. 2000 patents pending 6686-3.8 10/27/00 ep characteristics subject to change without notice. 1 of 17 block diagram sda scl s 0 /s 0 s 1 /s 1 s 2 /s 2 pp command decode and control logic program protect register x decode logic data register sector decode logic sectored high voltage control 32 8 memory array programming control logic 64k/32k/16k x24f064/032/016 8k/4k/2k x 8 bit serialflash ? memory with block lock ? protection features ? 1.8v to 3.6v or 5v univolt read and program power supply versions ? low power cmos active read current less than 1ma active program current less than 3ma standby current less than 1a ? internally organized 8k/4k/2k x 8 ? new programmable block lock protection software write protection programmable hardware write protect ? block lock (0, 1/4, 1/2, or all of the flash memory array) ? 2 wire serial interface ? bidirectional data transfer protocol ? 32 byte sector programming ? self timed program cycle typical programming time of 5ms per sector ? high reliability endurance: 100,000 cycles per byte data retention: 100 years ? available packages 8-lead pdip 8-lead soic (jedec) 14-lead tssop (x24f032/016) 20-lead tssop (x24f064) description the x24f064/032/016 is a cmos serialflash memory family, internally organized 8k/4k/2k x 8. the family features a serial interface and software protocol allow- ing operation on a simple two wire bus. device select inputs (s 0 , s 1 , s 2 ) allow up to eight devices to share a common two wire bus. a program protect register accessed at the highest address location, provides three new programming pro- tection features: software programming protection, block lock protection, and hardware programming protection. the software programming protection feature prevents any nonvolatile writes to the device until the wel bit in the program protect register is set. the block lock tm pro- tection feature allows the user to individually protect four blocks of the array by programming two bits in the pro- gramming protect register. the programmable hardware program protect feature allows the user to install each device with pp tied to v cc , program the entire memory array in place, and then enable the hardware program- ming protection by programming a ppen bit in the pro- gram protect register. after this, selected blocks of the array, including the program protect register itself, are permanently protected from being programmed. xicor serialflash memories are designed and tested for applications requiring extended endurance. inherent data retention is greater than 100 years. serialflash ? memory and block lock ? protection are trademarks of xicor, inc. a pplication n ote a v a i l a b l e an76 ? an78 ? an81 ? an87
x24f064/032/016 characteristics subject to change without notice. 2 of 17 pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open col- lector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to the pull-up resistor selection graph at the end of this data sheet. device select (s 0 , s 0 , s 1 , s 1 , s 2 , s 2 ) the device select inputs are used to set the device select bits of the 8-bit slave address. this allows multi- ple devices to share a common bus. these inputs can be static or actively driven. if used statically they must be tied to v ss or v cc as appropriate. if actively driven, they must be driven with cmos levels (driven to v cc or v ss ). program protect (pp) the program protect input controls the hardware program protect feature. when held low, hardware program protection is disabled and the x24f064/032/ 016 can be programmed normally. when this input is held high, and the ppen bit in the program protect register is set high, program protection is enabled, and nonvolatile writes are disabled to the selected blocks as well as the program protect register itself. pin names pin configuration symbol description s 0 , s 0 , s 1 , s 1 , s 2 , s 2 device select inputs sda serial data scl serial clock pp program protect v ss ground v cc supply voltage nc no connect v cc pp scl sda s 0 s 1 s 2 v ss 1 2 3 4 8 7 6 5 8-lead dip & soic X24F016 v cc pp nc nc s 0 s 1 nc nc 1 2 3 4 14 13 12 11 14-lead tssop nc nc 510 scl s 2 69 sda v ss 78 v cc pp scl sda s 0 s 1 s 2 v ss 1 2 3 4 8 7 6 5 8-lead dip & soic x24f032 v cc pp nc nc s 0 s 1 nc nc 1 2 3 4 14 13 12 11 14-lead tssop nc nc 510 scl s 2 69 sda v ss 78 v cc pp scl sda nc s 1 s 2 v ss 1 2 3 4 8 7 6 5 8-lead dip & soic x24f064 pp v cc pp nc nc nc s 1 nc 1 2 3 4 20 19 18 17 20-lead tssop nc nc 516 nc nc 615 scl s 2 714 scl nc 813 nc nc 912 nc nc 10 11
x24f064/032/016 characteristics subject to change without notice. 3 of 17 device operation the x24f064/032/016 supports a bidirectional bus ori- ented protocol. the protocol de?nes any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data trans- fers, and provide the clock for both transmit and receive operations. therefore, the x24f064/032/016 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figures 1 and 2. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the x24f064/032/016 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. figure 1. data validity figure 2. definition of start and stop scl sda data stable data change scl sda start bit stop bit stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 3. the x24f064/032/016 will respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the x24f064/032/016 will respond with an acknowledge after the receipt of each subsequent eight-bit word. in the read mode the x24f064/032/016 will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the x24f064/ 032/016 will continue to transmit data. if an acknowledge is not detected, the device will terminate further data transmissions. the master must then issue a stop condi- tion to return the x24f064/032/016 to the standby power mode and place the device into a known state.
x24f064/032/016 characteristics subject to change without notice. 4 of 17 figure 3. acknowledge response from receiver scl from master data output from transmitter 1 89 from receiver start acknowledge data output device addressing following a start condition the master must output the address of the slave it is accessing (see figure 4). the next two bits are the device select bits. a system could have up to eight x24f032/016s on the bus or up to four 24f064s on the bus. the device addresses are de?ned by the state of the s 0 , s 1 , and s 2 inputs. note some of the slave addresses must be the inverse of the corresponding input pin. figure 4. slave address also included in the slave address is an extension of the arrays address which is concatenated with the eight bits of address in the sector address ?eld, providing direct access to the entire serialflash memory array. the last bit of the slave address de?nes the operation to be performed. when set high a read operation is selected, when set low a program operation is selected. following the start condition, the x24f064/032/016 moni- tors the sda bus comparing the slave address being transmitted with its slave address device type identi?er. upon a correct comparison of the device select inputs, the x24f064/032/016 outputs an acknowledge on the sda line. depending on the state of the r/w bit, the x24f064/ 032/016 will execute a read or program operation. programming operations the x24f064/032/016 offers a 32-byte sector program- ming operation. for a program operation, the x24f064/ 032/016 requires a second address ?eld. this ?eld con- tains the address of the ?rst byte in the sector. upon receipt of the address, comprised of eight bits, the x24f064/032/016 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. the master then transmits 31 more bytes. after the receipt of each byte, the x24f064/032/ 016 will respond with an acknowledge. after the receipt of each byte, the ?ve low order address bits are internally incremented by one. the high order bits of the sector address remain constant. if the master should transmit more or less than 32 bytes prior to generating the stop condition, the contents of the sector cannot be guaranteed. all inputs are disabled until completion of the internal program cycle. refer to figure 5 for the address, acknowledge and data transfer sequence. s 2 r/w sector address s 1 a12 a11 a10 device select high order a9 a8 x24f064 s 2 r/w sector address s 1 s 0 a11 a10 device select high order a9 a8 x24f032 1 r/w sector address s 2 s 1 s 0 a10 device select high order a9 a8 X24F016 device identifier type
x24f064/032/016 characteristics subject to change without notice. 5 of 17 figure 5. sector programming s t a r t slave address s t o p a c k a c k a c k a c k a c k data n + 1 sector address data n s p data n + 31 bus activity: master sda line bus activity: X24F016/032/064 acknowledge polling the max write cycle time can be signi?cantly reduced using acknowledge polling. to initiate acknowledge polling, the master issues a start condition followed by the slave address byte for a write or read operation. if the device is still busy with the high voltage cycle, then no ack will be returned. if the device has completed the write operation, an ack will be returned and the host can then proceed with the read or write operation. refer to flow 1. flow 1. ack polling sequence program operation completed enter ack polling issue start issue slave address and r/w = 0 ack returned? next operation a write? issue sector address proceed issue stop no yes yes proceed issue stop no
x24f064/032/016 characteristics subject to change without notice. 6 of 17 read operations read operations are initiated in the same manner as program operations with the exception that the r/w bit of the slave address is set high. there are three basic read operations: current address read, random read and sequential read. it should be noted that the ninth clock cycle of the read operation is not a dont care. to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. current address read internally, the x24f064/032/016 contains an address counter that maintains the address of the last byte read, incremented by one byte. therefore, if the last read was from address n, the next read operation accesses data from address n + 1. upon receipt of the slave address with the r/w set high, the x24f064/ 032/016 issues an acknowledge and transmits the eight-bit word. the read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. refer to figure 6 for the sequence of address, acknowledge and data transfer. figure 6. current address read random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set high, the master must ?rst perform a dummy write opera- tion. the master issues the start condition, and the slave address with the r/w bit set low, followed by the byte address it is to read. after the byte address acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set high. this will be followed by an acknowledge from the x24f064/032/016 and then by the eight-bit byte. the read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. refer to figure 7 for the address, acknowledge and data transfer sequence. s t a r t slave address a c k s bus activity: master sda line bus activity: X24F016/032/064 data s t o p p figure 7. random read s t a r t slave address a c k a c k s s t a r t slave address byte address n s a c k data n s t o p p bus activity: master sda line bus activity: X24F016/032/064 sequential read sequential reads can be initiated as either a current address read or random access read. the ?rst byte is transmitted as with the other modes, however, the master now responds with an acknowledge, indicating it requires additional data. the x24f064/032/016 con- tinues to output data for each acknowledge received. the read operation is terminated by the master; by not responding with an acknowledge and then issuing a stop condition. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. at the end of the address space, the counter rolls over to 0 and the x24f064/032/016 continues to output data for each acknowledge received. refer to figure 8 for the address, acknowledge and data transfer sequence.
x24f064/032/016 characteristics subject to change without notice. 7 of 17 figure 8. sequenctial read figure 9. typical system configuration slave address s t o p a c k a c k a c k a c k data n data n+1 data n+2 data n+x p bus activity: master sda line bus activity: X24F016/032/064 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver pull-up resistors sda scl v cc program protect register the program protect register (ppr) is accessed at the highest address of each device: x24f064 = 1fff x24f032 = 0fff X24F016 = 07ff program protect register ppr.1 = wel C write enable latch (volatile) 0 = write enable latch reset, programming disabled 1 = write enable latch set, programming enabled if wel = 0 then no ack after ?rst byte of input data. ppr.2 = rwel C register write enable latch (volatile) 0 = register write enable latch reset, programming disabled 1 = register write enable latch set, programming enabled ppr.3, ppr.4 = bl0, bl1 C block lock bits (nonvolatile) (see block lock bits section for de?nition) ppr.7 = ppen C programming protect enable bit (nonvolatile) (see programmable hardware program protect section for de?nition) writing to the program protect register the program protect register is written by performing a write of one byte directly to the highest address loca- tion. during normal sector programming, the byte in the array at the highest address will be written instead of the program protect register (assuming program- ming is not disabled by the block lock register). the state of the program protect register can be read by performing a random read at the highest address location at any time. if a sequential read starting at any other address than the highest address location is performed, the contents of the byte in the array at the highest address location is read out instead of the program protect register. 7 6543 2 10 wpen 0 0 bp1 bp0 rwel wel 0
x24f064/032/016 characteristics subject to change without notice. 8 of 17 wel and rwel are volatile latches that power-up in the low (disabled) state. a write to any address other than the highest address location, where the program protect register is located, will be ignored (no ack) until the wel bit is set high. the wel bit is set by writing 0000001x to the highest address location. once set, wel remains high until either reset (by writing 00000000 to the highest address location) or until the part powers-up again. the rwel bit controls writes to the block lock bits. rwel is set by ?rst setting wel = 1 and then writing 0000011x to the highest address location. rwel must be set in order to change the block lock bits (bl0 and bl1) or the ppen bit. rwel is reset when the block lock or ppen bits are changed, or when the part powers-up again. programming the bl or ppen bits a three step sequence is required to change the non- volatile block lock or program protect enable: 1) set wel = 1 (write 00000010 to the highest address location, volatile write cycle) (start) 2) set rwel = 1 (write 00000110 to the highest address location, volatile write cycle) (start) 3) set bl1, bl0, and/or ppen bits (write w00yz010 to the highest address location) w = ppen, y = bl1, z = bl0, (stop) step 3 is a nonvolatile program cycle, requiring 10ms to complete. rwel is reset (0) by this program cycle, requiring another program cycle to set rwel again before the block lock bits can be changed. rwel must be 0 in step 3; if w00yz110 is written to the high- est address location, rwel is set but ppen, bl1 and bl0 are not changed (the device remains at step 2). block lock bits the block lock bits bl0 and bl1 determine which blocks of the memory are write-protected: table 1. block lock bits programmable hardware program protect the program protect (pp) pin and the program protect enable (ppen) bit in the program protect register control the programmable hardware program protect feature. hardware program protection is enabled when the pp pin and the ppen bit are both high , and dis- abled when either the pp pin is low or the ppen bit is low. when the chip is hardware program-protected, nonvolatile programming is disabled, including the pro- gram protect register, the bl bits and the ppen bit itself, as well as to block locked sections in the mem- ory array. only the sections of the memory array that are not block locked can be written. note that since the ppen bit is program-protected, it cannot be changed back to a low state, and program protection is disabled as long as the pp pin is held high. table 2 de?nes the program protection status for each state of ppen and pp. bl1 bl0 array locked 0 0 none 0 1 upper 1/4 1 0 upper 1/2 1 1 full array (wpr not included) table 2. program protect status table pp ppen memory array (not block locked) memory array (block locked) bl bits ppen bit 0 x programmable locked programmable programmable x 0 programmable locked programmable programmable 1 1 programmable locked locked locked
x24f064/032/016 characteristics subject to change without notice. 9 of 17 absolute maximum ratings temperature under bias x24f064/032/016 ..............................C65 to +135c storage temperature .............................C65 to +150c voltage on any pin with respect to v ss .......C1v to +7v d.c. output current ............................................... 5ma lead temperature (soldering, 10 seconds)........ 300c comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; and the functional opera- tion of the device (at these or any other conditions above those indicated in the operational sections of this speci?cation) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0 c +70 c extended C20 c +85 c industrial C40 c +85 c supply voltage limits x24f064/032/016 1.8v to 3.6v x24f064/032/016C5 4.5v to 5.5v d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) capacitance t a = +25c, f = 1mhz, v cc = 2.7v notes: (1) must perform a stop command prior to measurement. (2) v il min. and v ih max. are for reference only and are not 100% tested. (3) this parameter is periodically sampled and not 100% tested. symbol parameter limits units test conditions min. max. i cc1 v cc supply current (read) 1 ma scl = v cc x 0.1/v cc x 0.9 levels @ 100khz, sda = open, all other inputs = v ss or v cc C 0.3v i cc2 v cc supply current (write) 3 ma i sb1 (1) v cc standby current 1 m a scl = sda = v cc , all other inputs = v ss or v cc C 0.3v, v cc = 3.6v i sb2 (1) v cc standby current 10 m a scl = sda = v cc , all other inputs = v ss or v cc C 0.3v, v cc = 5v 10% i li input leakage current 10 m av in = v ss to v cc i lo output leakage current 10 m av out = v ss to v cc v ll (2) input low voltage C1 v cc x 0.3 v v ih (2) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 3ma symbol parameter max. units test conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (s 1 , s 2 , scl) 6 pf v in = 0v
x24f064/032/016 characteristics subject to change without notice. 10 of 17 a.c. conditions of test equivalent a.c. load circuit input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 5v 1533 w 100pf output 2.7v 1533 w 100pf output a.c. operating characteristics (over the recommended operating conditions, unless otherwise speci?ed.) read & write cycle limits power-up timing (4) notes: (4) t pur and t puw are the delays required from the time v cc is stable until the speci?ed operation can be initiated. these parameters are periodically sampled and not 100% tested. symbol parameter min. max. units f scl scl clock frequency 0 100 khz t i noise suppression time constant at scl, sda inputs 100 ns t aa scl low to sda data out valid 0.3 3.5 m s t buf time the bus must be free before a new transmission can start 4.7 m s t hd:sta start condition hold time 4 m s t low clock low period 4.7 m s t high clock high period 4 m s t su:sta start condition setup time (for a repeated start condition) 4.7 m s t hd:dat data in hold time 0 m s t su:dat data in setup time 250 ns t r sda and scl rise time 1 m s t f sda and scl fall time 300 ns t su:sto stop condition setup time 4.7 m s t dh data out hold time 300 ns symbol parameter max. units t pur power-up to read operation 1 ms t puw power-up to write operation 5 ms
x24f064/032/016 characteristics subject to change without notice. 11 of 17 bus timing program cycle limits notes: (5) typical values are for t a = 25c and nominal supply voltage (5v). (6) t wr is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. it is the maximum time the device requires to automatically complete the internal write operation. the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write cycle. during the write cycle, the x24f064/032/016 bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. bus timing symbol parameter min. typ. (5) max. units t wc (6) programmable cycle time 5 10 ms t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high scl sda 8th bit word n ack t wc stop condition start condition
x24f064/032/016 characteristics subject to change without notice. 12 of 17 guidelines for calculating typical values of bus pull-up resistors symbol table 120 100 80 40 60 20 20 40 60 80 100 120 0 0 resistance (k w ) bus capacitance (pf) min. resistance max. resistance r max = c bus t r r min = i ol min v cc max =1.2k w waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance
x24f064/032/016 characteristics subject to change without notice. 13 of 17 packaging information note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional .073 (1.84) max. 0.325 (8.25) 0.300 (7.62) plane
x24f064/032/016 characteristics subject to change without notice. 14 of 17 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 - 8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in p arentheses in millimeters) 0.250" 0.050"typical 0.050" typical 0.030" typical 8 places footprint
x24f064/032/016 characteristics subject to change without notice. 15 of 17 packaging information note: all dimensions in inches (in p arentheses in millimeters) 14-lead plastic, tssop, package type v see detail a .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 - 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
x24f064/032/016 characteristics subject to change without notice. 16 of 17 packaging information note: all dimensions in inches (in p arentheses in millimeters) 20-lead plastic, tssop, package type v see detail a .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 - 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
x24f064/032/016 characteristics subject to change without notice. 17 of 17 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?cation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devi ces from patent infringement. xicor, inc. makes no warranty of merchantability or ?tness for any purpose. xicor, inc. reserves the right to discontinue production and change s peci?cations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?cant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ordering information part mark convention device x24fxxx x x temperature range blank = commercial = 0 c to +70 c e = extended = C20 c to +85 c package p = 8-lead plastic dip s = 8-lead soic (jedec) v = 14-lead tssop x24f032 X24F016 x24f064 x24f064 x24f032 X24F016 v cc range blank = 1.8v to 3.6v 5 = 4.5v to 5.5v Cx p = 8-lead plastic dip s = 8-lead soic (jedec) v = 20-lead tssop i = industrial = C40 c to +85 c p = 8-lead plastic dip blank = 8-lead soic (jedec) blank = 1.8v to 3.6v, 0 c to +70 c e = 1.8v to 3.6v, C20 c to +85 c x24fxxx x x v = 14/20-lead tssop x24f064 x24f032 X24F016 5 = 4.5v to 5.5v, 0 c to +70 c i5 = 4.5v to 5.5v, C40 c to +85 c

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